In the fabrication of semiconductor devices, defects in the circuits formed are frequently caused by leakage current problems. The determination of a tolerance range for the leakage current in an IC circuit is therefore an important aspect in the design and fabrication of IC devices. During the design of an IC circuit in a semiconductor chip, a design margin or a process window is normally incorporated in the circuit design such that a circuit thus formed operates properly within the design margin and the process window. A weak circuit, or a weak link in the IC circuit such as that frequently observed at a node results when such design margin or process window is not properly provided during the circuit design process.
The ability of identifying and locating potentially weak circuits in a VLSI product, for instance, in a logic IC chip or in a memory chip prior to a failure of the product is therefore an important step in the quality control and reliability testing of such products. For instance, in a test procedure designed for testing the leakage current in a circuit, the IC circuit may pass under certain conditions, but may functionally fail or marginally fail under other conditions. When the driving voltage is increased in the circuit, the circuit then passes its functionality test. When this occurs, it is an indication that the internal driving capability in the IC circuit is insufficient and therefore, when the voltage becomes lower, the circuit can not pass its functionality test. In designing such a reliability test, it is always a problem that the exact locations of the weak circuits in the IC chip cannot be easily located or identified. In other words, it is very difficult to pin point the circuits within which the driving current is not high enough. While scanning electron microscopy is a well established technique in studying surfaces of an object, an optical image obtained by the technique does not reveal any information on the circuit contained inside the IC chip. Traditionally, the detection work can only be carried out by the cooperative effort between a product engineer and a circuit designer using functionality testing apparatus, computer simulation and design layout to find the potential failure sites. Such debugging work on a wafer is extremely time consuming, i.e., takes as long as two months for the task on a 6-inch wafer.
It is therefore an object of the present invention to provide a method for locating weak circuits in an IC chip that does not have the drawbacks and shortcomings of the conventional reliability testing methods.
It is another object of the present invention to provide a method for locating a weak circuit that has insufficient driving current in an IC chip which can be readily carried out in an scanning electron microscope.
It is a further object of the present invention to provide a method for locating a weak current that has insufficient driving current in an IC chip by irradiating the circuit with an electron beam that carries a loading current of not less than 0.01 .mu.A.
It is another further object of the present invention to provide a method for locating a weak circuit that has insufficient driving current in an IC chip by scanning the chip surface point-to-point with an electron beam that carries a loading current between about 0.01 .mu.A and about 100 .mu.A.
It is still another object of the present invention to provide a method for locating a weak circuit that has insufficient driving current in an IC chip by first selecting a threshold current as the loading current for an electron beam which causes failure in a circuit upon irradiation by the electron beam.
It is yet another object of the present invention to provide a method for identifying a weak node that has insufficient driving current in an IC chip by scanning an electron beam on the chip and pulling down a driving current at the node to cause a functional failure of the circuit.
It is yet another further object of the present invention to provide a method for identifying a weak node that has insufficient driving current in an IC chip by first determining a threshold current of the electron beam that is used to scan the IC chip which causes failure of the circuit and then scanning the entire IC chip surface by the threshold current to locate other potentially weak circuits.
It is still another further object of the present invention to provide a method for identifying a weak node that has insufficient driving current in an IC chip by first causing functional failure in a circuit by irradiating the circuit with an electron beam that has a threshold current and then marking the failed circuit by an imaging means in the scanning electron microscope.
It is yet another further object of the present invention to provide a method for locating a weak circuit that has insufficient driving current in an IC chip by first scanning the surface of the IC chip at about 50.times. magnification in a scanning electron microscope for locating a failure site and then, scanning the failure site at a 2,000.times. magnification for showing the circuit failed.